1. Field of the Invention
The present invention relates to a technique of signal transmission between devices such as multiple processors and memories (for example, between digital circuits constructed by CMOSs or between their functional blocks) in an information processing apparatus, and in particular to a technique for speeding up bus transmission which a plurality of elements are connected to a same transmission line for transferring data. In particular, the present invention relates to a bus to which a plurality of memory modules and a memory controller are connected and to a system using that bus.
2. Description of Related Art
As a bus system that is connected with many nodes and intended for high-speed data transfer, is mentioned a non-contact bus line of Japanese Unexamined Patent Laid-Open No. 7-141079 (U.S. Pat. No. 5,638,402). FIG. 5 shows the basic system of the conventional technique. In this technique, data transfer between two nodes is realized by utilizing crosstalk, i.e., using a directional coupler. Namely, FIG. 5 shows a technique in which transfer between a bus master 10-1 and slaves 10-2–10-8 is carried out utilizing crosstalk between two lines, i.e., between the line 1-1 and a line 1-2–1-8. The technique of FIG. 5 is suitable for transfer between the bus master 10-1 and the slaves 10-2–10-8, or data transfer between a memory controller and memories.
However, in the conventional technique of 7-141079 (U.S. Pat. No. 5,638,402), the line length occupied by a directional coupler decides module intervals. Accordingly, in order to shorten the module intervals, it is necessary to shorten the line length of the directional coupler. However, shorter line length becomes a cause of reducing the transmission efficiency, i.e., degree of coupling, and thus, it is impossible to make each interval less than certain length. Thus, a first problem is to realize high-density mounting of memories by making intervals between memory modules smaller.
A second problem is that, as transmission speed becomes higher in high-speed data transmission, waveform distortion increases owing to frequency-dependent effects such as the skin effect. This appears as a phenomenon that pulse waveform becomes dull at its rising and falling shoulders, and owing to this influence, appears as an increase of skew when a receiver takes in the pulse waveform. Namely, since the shoulders of the pulse waveform inputted into the receiver become dull, time when a signal exceeds or falls short of the receiver's reference voltage (Vref) increases. As a result, receiver's take-in time increases, causing the increase of the skew.
The reason why the skin effect makes the shoulders of the pulse dull is described as follows.
A high-speed pulse has a high-frequency component depending on the reciprocal of its transition (rise or fall) time. For example, the frequency bank (fknee) of a pulse having the transition time Tr can be written by the following equation:fknee=0.35/Tr  (1)
Accordingly, when it is assumed that a pulse of 1 Gbps is transmitted and 30% of it is the transition time, then, fknee=0.35/(0.3 [ns])˜1 GHz. In this case, resistance increase owing to the skin effect is calculated as follows.
The volume resistivity ρ of copper at 20 [° C.] is 1.72*10^−8 [Ω·m]. In the case of a standard line (linewidth 0.1 [mm] and line thickness 0.030 [mm]) in a board, DC resistance becomes 5.7 [mΩ/mm]. Here, “^” expresses the power. Further, resistance per unit length owing to the skin effect is:r=2.6×10^−6√{square root over (f)}[Ω/mm]  (2)and, at 1 GHz, it becomes:r=82[mΩ/mm].Thus, in comparison with the DC resistance 6 [mΩ/mm], the resistance in the transmission time increases 13 times. Namely, the high resistance appears only at the transition time, and this leads to the dull wave waveform. This is because a resistance component becomes larger as the frequency becomes higher, thus having larger effects at rising and falling times. As a technique for overcoming this, a driver can be used to make the pulse waveform steeper at the transition (rise and fall) times. For example, an article, “Limits of Electrical Signaling (Transmitter Equalization)”; IEEE HOT interconnect V (1997, 9/21–23), pp. 48 describes an equalizer system using DAC (Digital Analog Converter) of a driver (transmitter). This is realized in the driver by changing transition waveform steeply all the more when the quantity of dullness is larger. In the case of using this technique, the driver becomes complex and it is difficult to mount many devices on LSI.
As a third problem, a plurality of memories have different line lengths depending on their distances from a memory controller. This causes time differences in read and write data. Data arrival times are different depending on chip locations, and its correction makes system design very difficult. Thus, removal of these time differences is a problem.